Silicon and software solutions for the convergence of sense and communications
Conventional Architectures For Communications & Sense
Flexibility vs Performance
Energy Efficiency (MOP/mW)
| ASICS | GPUs/DSPs | FPGAs |
|---|---|---|
| Limited flexibility | Not design for low-latency or wideband | Difficult to program |
| $100M+ development budget | 10x- higher cost | 20x-100x higher cost |
| 3-year time-to-market | 10x – 100x higher power | 20x higher power |
| Limited product life | Proprietary ISA | Designed for low performance |
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- Rapid evolution of functionality (standards, use-cases)
- No opportunity for resource sharing (DDR, antennas)
- Need for ultrawide bandwidth & low latency operation
Options are limited to Inflexible ASICs or Expensive & Power-Hungry FPGAs
Xcelerium’s Solution Architected For Communications & Sense
Flexibility vs Performance
Energy Efficiency (MOP/mW)
10x Lower Power than GPUs
10x Smaller Die than FPGAs
75% reduction in TTM
- Flexible and C-programable (based on RISCV)
- Designed for ultrawide bandwidths
- Intrinsically low latency
- Unified architecture for communications, sensor processing and AI
- Power, performance and form factor of ASICs